{
  "source_commit": "2a8be044006471c4fdbdef9f0993a99a716fe8cf",
  "started_utc": "2026-11-13T07:43:54.552560+00:00",
  "reason": "A plain slow-mode baseline can miss static port cancellation; add standard DC-response directions for a stronger fair comparator. No original data, gates, physical parameters or input signals changed.",
  "source_hashes": {
    "thin_film/scripts/edge_memory/dc_control.py": "953a35b8b5755baceb719c2d205f299613040d0a2b5a2d2094b84610d2b9f9ee",
    "thin_film/scripts/edge_memory/port.py": "04f70a8832abf2a2b6ad01eb01e96f49a6b33aac7aca66351dbc36e2188a3a4b"
  },
  "caps": [
    5,
    9,
    17
  ],
  "cases": [
    "L100_h2_slow_pulse",
    "L100_h2_fast_pulse",
    "L100_h2_chirp",
    "L100_h6_slow_pulse",
    "L100_h6_fast_pulse",
    "L100_h6_chirp",
    "L200_h2_slow_pulse",
    "L200_h2_fast_pulse",
    "L200_h2_chirp",
    "L200_h6_slow_pulse",
    "L200_h6_fast_pulse",
    "L200_h6_chirp",
    "L300_h2_slow_pulse",
    "L300_h2_fast_pulse",
    "L300_h2_chirp",
    "L300_h6_slow_pulse",
    "L300_h6_fast_pulse",
    "L300_h6_chirp"
  ],
  "whole_budget_s": 300
}